1. The Field of the Invention
The present invention relates to the field of data transmitting and receiving interface devices and methods. More particularly, the present invention relates to a system and method for directly transferring data between a host system, such as a personal computer, and a digital signal processor for performing, among other things, modulation/demodulation.
2. Present State of the Art
With the advances and the ubiquitous nature of computer and telephone communication systems requiring expanded data transfer and processing capabilities, there is a continuing demand for improving the transfer of data from a host system such as a computer system, to a communication network such as a telephone infrastructure, via a communication module. For example, the increased transfer of voice, sound, and image data over networks such as the Internet require high speed data processing capabilities at very high data transfer rates. Such advanced technological requirements place demands on hardware and software components and require efficient processing and transport of data through such interfacing communication modules.
A conventional communication module implementation generally includes a modem (modulator/demodulator) operably coupled with a host system such as a computer. The host system provides the user interface for the generation or consumption (viewing, hearing, or storing) of transfer data by a user of the host system. Prior art configurations have connected host systems with a communication module such as a modem via a serial or parallel port or interface.
A traditional communication module such as a modem may include a standard Universal Asynchronous Receiver/Transmitter (UART) or UART emulator in which the format of data is converted. A UART device essentially converts data between parallel and serial formats depending upon whether the host system is transmitting or receiving data. Data on the host system is stored and operated upon in parallel form and must therefore be converted to serial form for transmission from the host system into the communication network.
FIG. 1 represents a prior art configuration of network interface configuration 100 comprising a host system 102, a UART 106, and a modem 120 for interfacing with communication network 128. Host system 102 is further comprised of a host bus 104 which is traditionally a parallel interface for support devices such as processors, memory, and other peripheral devices such as UART 106. UART 106 traditionally interfaces with host system 102 via host bus 104 and receives data for transmission in parallel form as represented by transmit path 108. UART 106 also provides received data to host system 102 in parallel form as represented by receive path 110. Status and control information (e.g., status regarding whether transmit data has been forwarded or whether pending receive data is awaiting retrieval by host system 102) are also provided by UART 106 in control registers 118 as represented by control path 112. Data interfacing outside UART 106 traditionally occurs via a serial port 122, and in many personal computers, UART 106 is internally housed and presents a serial COM port for interfacing with serial peripherals.
In FIG. 1, the primary function of modem 120 is to allow the transmission and reception of data over a telephone medium such as communication network 128. Modem 120 traditionally comprises a UART 124 and a DSP 126. UART 124 reconverts transmit data back from serial format to parallel format for processing by DSP 126. UART 124 also converts receive data from parallel to serial for transferring to UART 106. DSP 126 provides modulation and demodulation of data for transceiving over channel 130 with communication network 128. Transceived waveforms comprise analog waveforms which are modulated and demodulated for carrying data over communication network 128.
Traditional UARTs in a modem device typically process data in block mode and when processing is completed such as transmission of transmit data or receipt and demodulation of receive data, an interrupt is sent to the host system or, alternatively, a status is posted in a control register which may be polled by the host system to signify a request for the transfer of additional data or to inform the host system to retrieve the available data. By way of example, a 1-byte UART would transfer a single byte of data for each interrupt request or status posted and reacted upon. UARTs operate, for example in a transmit mode, by transferring a parallel byte over the host bus to a holding register from which it may be serially transferred. When the holding register becomes empty, a subsequent interrupt invites the host system to transfer an additional byte of data.
Advances in the UART art created a conventional UART having a plurality (i.e., usually 16) buffers which operate as First In First Out (FIFO) buffers (e.g., transmit buffers 114, and receive buffers 116 both of FIG. 1) providing interim storage of additional bytes of data prior to initiating an interrupt to the host system. Further advances in the prior art resulted in UART emulation wherein UART 106 and modem 120 were effectively combined into a single function and the conversion of parallel data present in UART 106 into serial data for transmission between UART 124 over serial port 122 was discontinued. It should be recognized that if UART 106 and modem 120 are merged, serialization of transferred data becomes unnecessary. Although serialization in a merged architecture is abrogated, the merged configuration must still present a UART-appearance to host system 102 to retain compatibility with existing drivers and control functions pertaining to the transfer of data between host system 102 and communication network 128.
Conventional UARTs may be adequate for lower data rate transfers of information, however, as transmission data rates increase due to increased bandwidth appetites, piecemeal transfers of data between a host system and a communication module such as a modem become increasingly more burdensome upon host systems that become expected to service interrupt requests nearly incessantly for what have become typical data transfers over communication network 128. Depending upon the particular software applications being concurrently serviced by the host system, the host system may not have sufficient time to service all of the processing interruptions requested by peripherals.
Additionally, significant latency is introduced in transfers of data between a host system and communication network by any required interim handling of data. As discussed above, traditionally, data passed in parallel form from a host system to holding registers in a UART. These holding registers were then in turn serviced internally by the UART whereupon the data in the registers were serially transferred to another holding register of the modem""s UART. The modem""s UART needed to retain the data until such data was directly requested by the DSP or until such data may be again transferred to a holding memory accessible by the DSP. Only after the holding registers were serviced by the passing of the data through the stages of the data pipeline, could subsequent data enter the pipeline from the host system. The continuous shuffling of data among intermediate holding registers degradates performance throughput of a communication module because of iterative shifting and relocation of transmit or receive data.
Thus, it is desirable to maximize the data transfer rate between a host system and a communication network via a communication module and further to minimize or control the interruptions to the host system in servicing such data transfers.
It is, therefore, an object of the present invention to provide a data communication module for transceiving data between a host system and a communication network that is capable of directly transferring or queuing transmit data from the host system to the DSP""s memory and for providing access by the host system to receive data upon completion of processing (e.g., demodulation) by the DSP.
Another object of the present invention is to accommodate the defining of the frequency of interruption to the host system by the communication module.
Yet another object of the present invention is to provide a communication module that complies with or presents the compatible appearance to the host system of a traditional UART.
Still another object of the present invention is to provide an emulated UART for directly facilitating the transfer of data between the host system and the DSP providing processing of signals for a communication network.
Still yet another object of the present invention is to provide a method for asynchronously transceiving data between a host system and a communication network without introducing latency due to relocation of data in a communication module.
Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims.
To achieve the foregoing objects, and in accordance with the invention as embodied and broadly described herein, a method and communication module for asynchronously transmitting transmit data and receiving receive data between a host system and a communication network is provided.
The method is performed by and the communication module is comprised of an emulated UART which provides an efficient conduit between: a host system, a digital signal processor (DSP) which provides modulation/demodulation services, and a DSP memory. In the present invention, transceiver buffers comprised of individual transmit and receive buffers are initialized within the DSP memory by defining read and write pointers in addition to buffer boundaries.
When a host system possesses transmit data, such transmit data is queued directly from a host system to a transmit buffer in a DSP memory. The emulated UART facilitates Direct Memory Access-like (DMA) transfer of transmit data directly from the host system to the transmit buffers resident within the DSP memory. Processing of the transmit data then proceeds with the DSP performing modulation, and optionally data compression, followed by transmission of the processed transmit data.
When a DSP receives previously processed (i.e., modulated and optionally data compressed) receive data, the DSP processes such data and stores or queues the receive data in the receive buffer of the DSP memory. When a quantity of receive data exceeds a definable threshold level, the emulated UART notifies the host system either through the use of interrupts or by posting a status in a control register that may be polled by the host system. When requested by the host system, the emulated UART directly transfers the receive data from the DSP memory to the host system.
These and other objects and features of the present invention will be more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth herein.